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1 ltc3404 3404fb applicatio s u features descriptio u typical applicatio u high efficiency: up to 95% very low quiescent current: only 10 a during operation 600ma output current at v in = 3.3v 2.65v to 6v input voltage range 1.4mhz constant frequency operation no schottky diode required low dropout operation: 100% duty cycle synchronizable from 1mhz to 1.7mhz selectable burst mode operation or pulse skipping mode 0.8v reference allows low output voltages shutdown mode draws < 1 a supply current 2% output voltage accuracy current mode control for excellent line and load transient response overcurrent and overtemperature protected available in 8-lead msop package the ltc 3404 is a high efficiency monolithic synchro- nous buck regulator using a constant frequency, current mode architecture. supply current during operation is only 10 a and drops to < 1 a in shutdown. the 2.65v to 6v input voltage range makes the ltc3404 ideally suited for single li-ion battery-powered applications. 100% duty cycle provides low dropout operation, extending battery life in portable systems. switching frequency is internally set at 1.4mhz, allowing the use of small surface mount inductors and capacitors. for noise sensitive applications the ltc3404 can be externally synchronized from 1mhz to 1.7mhz. burst mode operation is inhibited during synchronization or when the sync/mode pin is pulled low, preventing low frequency ripple from interfering with audio circuitry. the internal synchronous switch increases efficiency and eliminates the need for an external schottky diode. low output voltages are easily supported with the 0.8v feed- back reference voltage. the ltc3404 is available in a space saving 8-lead msop package. for higher input voltage (11v abs max) applications, refer to the ltc1877 data sheet. cellular telephones wireless and dsl modems personal information appliances portable instruments distributed power systems battery-powered equipment high efficiency step-down converter 1.4mhz high efficiency monolithic synchronous step-down regulator efficiency vs output load current load (ma) 80 75 efficiency (%) 85 90 95 100 0.1 10 100 1000 3404 ta02 70 1 v in = 6v v in = 4.2v v in = 3.6v burst mode operation v out = 3.3v l = 4.7 h 22 f** cer 7 6 1 2 5 3 4 sw v fb ltc3404 gnd 4.7 h* 10 f*** cer 47pf v out ? 3.3v * ** *** ? toko d52lc a914byw-4r7m taiyo-yuden ceramic jmk325bj226mm taiyo-yuden ceramic lmk325bj106mn v out connected to v in for 2.65v < v in < 3.3v 887k 20pf 280k 3404 ta01 sync v in run i th v in 2.65v to 6v , lt, ltc and ltm are registered trademarks of linear technology corporation. burst mode is a registered trademark of linear technology corporation. all other trademarks are the property of their respective owners.
2 ltc3404 3404fb symbol parameter conditions min typ max units i vfb feedback current (note 4) 430 na v fb regulated output voltage (note 4) 0 c f t a f 85 c 0.784 0.8 0.816 v (note 4) e 40 c f t a f 85 c 0.74 0.8 0.84 v ) v ovl output overvoltage lockout ) v ovl = v ovl e v fb 20 50 110 mv ) v fb reference voltage line regulation v in = 2.65v to 6v (note 4) 0.05 0.2 %/v v loadreg output voltage load regulation measured in servo loop; v ith = 0.9v to 1.2v 0.1 0.5 % measured in servo loop; v ith = 1.6v to 1.2v e 0.1 e 0.5 % v in input voltage range 2.65 6 v i q input dc bias current (note 5) pulse skipping mode 2.65v < v in < 6v, v sync/mode = 0v, i out = 0a 400 700 r a burst mode operation v sync/mode = v in , i out = 0a 10 15 r a shutdown v run = 0v, v in = 6v 0 1 r a f osc oscillator frequency v fb = 0.8v 1.25 1.4 1.65 mhz v fb = 0v 200 khz f sync sync capture range 1.0 1.7 mhz i pll lpf phase detector output current sinking capability f pllin < f osc 6 20 40 r a sourcing capability f pllin > f osc e6 e20 e40 r a r pfet r ds(on) of p-channel mosfet i sw = 100ma 0.5 0.7 < r nfet r ds(on) of n-channel mosfet i sw = e100ma 0.6 0.8 < i pk peak inductor current v in = 3.3v, v fb = 0.7v, duty cycle < 35% 0.8 1.0 1.25 a i lsw sw leakage v run = 0v, v sw = 0v or 6v, v in = 6v 0.01 1 r a v sync/mode sync/mode threshold v sync/mode rising 0.3 1.0 1.5 v i sync/mode sync/mode leakage current 0.01 1 r a v run run threshold v run rising 0.3 0.7 1.5 v i run run input current 0.01 1 r a (note 1) input supply voltage (v in )...........................e 0.3v to 7v i th , pll lpf voltage ................................e 0.3v to 2.7v run, v fb voltages ...................................... e 0.3v to v in sync/mode voltage .................................. e 0.3v to v in sw voltage (dc) .......................... e 0.3v to (v in + 0.3v) p-channel mosfet source current (dc) ........... 800ma n-channel mosfet sink current (dc) ............... 800ma peak sw sink and source current ........................ 1.5a operating temperature range (note 2) ltc3404e/ltc3404i ........................... e40 c to 85 c ltc3404mp ...................................... e55 c to 125 c junction temperature (note 3) ............................ 125 c storage temperature range ................. e 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c the denotes specifications which apply over e40 c to 85 c, otherwise specifications are t a = 25 c. v in = 3.6v unless otherwise specified. absolute axi u rati gs w ww u package/order i for atio uu w electrical characteristics 1 2 3 4 8 7 6 5 top view ms8 package 8-lead plastic msop pll lpf sync/mode v in sw run i th v fb gnd t jmax = 125 c, v ja = 125 c/w order part number ms8 part marking consult ltc marketing for parts specified with wider operating temperature ranges. ltc3404ems8 ltc3404ims8 LTC3404MPMS8 ltkr ltcjr ltcxg order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/
3 ltc3404 3404fb note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3404e is guaranteed to meet performance specifications from 0 c to 85 c. specifications over the 40 c to 85 c operating temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3404i is guaranteed to meet performance specifications over the ?0 c to 85 c operating temperature range. the ltc3404mp is guaranteed to meet performance specifications over the ?5 c to 125 c operating temperature range. note 3: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formulas: t j = t a + (p d )(150 c/w) note 4: the ltc3404 is tested in a feedback loop which servos v fb to the balance point for the error amplifier (v ith = 1.2v). note 5: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. symbol parameter conditions min typ max units i vfb feedback current (note 4) 4 30 na v fb regulated output voltage (note 4) 0 c t a 125 c 0.784 0.8 0.816 v (note 4) 55 c t a 125 c 0.74 0.8 0.84 v v ovl output overvoltage lockout v ovl = v ovl ?v fb 20 50 110 mv v fb reference voltage line regulation v in = 2.65v to 6v (note 4) 0.05 0.2 %/v v loadreg output voltage load regulation measured in servo loop; v ith = 0.9v to 1.2v 0.1 1 % measured in servo loop; v ith = 1.5v to 1.2v 0.1 1 % v in input voltage range 2.65 6 v i q input dc bias current (note 5) pulse skipping mode 2.65v < v in < 6v, v sync/mode = 0v, i out = 0a 400 700 a burst mode operation v sync/mode = v in , i out = 0a 10 15 a shutdown v run = 0v, v in = 6v 0 1 a f osc oscillator frequency v fb = 0.8v 1.25 1.4 1.65 mhz v fb = 0v 200 khz f sync sync capture range 1.0 1.7 mhz i pll lpf phase detector output current sinking capability f pllin < f osc 6 20 40 a sourcing capability f pllin > f osc ? 20 40 a r pfet r ds(on) of p-channel mosfet i sw = 100ma 0.7 r nfet r ds(on) of n-channel mosfet i sw = 100ma 0.8 i pk peak inductor current v in = 3.3v, v fb = 0.7v, duty cycle < 35%, 0.4 1.0 1.1 a t a = 125 c v in = 4v, v fb = 0.7v, duty cycle < 35%, 0.8 1.2 a t a = 125 c i lsw sw leakage v run = 0v, v sw = 0v or 6v, v in = 6v 3 a v sync/mode sync/mode threshold v sync/mode rising 0.3 1.5 v i sync/mode sync/mode leakage current 1 a v run run threshold v run rising 0.3 1.5 v i run run input current 1 a the denotes specifications which apply over ?5 c to 125 c, otherwise specifications are t a = 25 c. v in = 3.6v unless otherwise specified. electrical characteristics
4 ltc3404 3404fb output current (ma) 70 efficiency (%) 80 90 65 75 85 0.1 10 100 1000 3404 g04 60 1 v in = 3v v in = 6v v out = 1.8v l = 4.7 h v in = 4.2v v in = 3.6v typical perfor a ce characteristics uw oscillator frequency vs temperature efficiency vs output current temperature ( c) ?0 reference voltage (v) 0.814 0.809 0.804 0.799 0.794 0.789 0.784 25 75 3404 g05 ?5 0 50 100 125 v in = 3.6v oscillator frequency vs supply voltage reference voltage vs temperature output voltage vs load current output current (ma) 80 75 efficiency (%) 85 90 95 100 0.1 10 100 1000 3404 g4a 70 65 1 v in = 6v v in = 3.6v v out = 3.1v l = 4.7 h v in = 4.2v efficiency vs output current temperature ( c) ?0 frequency (mhz) 1.55 1.50 1.45 1.40 1.35 1.30 1.25 100 75 3404 g06 ?5 0 50 25 125 v in = 3.6v supply voltage (v) oscillator frequency (mhz) 1.25 1.35 1.30 8 3404 g07 2 4 6 1.55 1.50 1.45 1.40 load current (ma) 0 1.75 1.76 1.77 output voltage (v) 1.78 1.80 1.81 1.82 200 400 3404 g08 1.79 600 800 1.83 pulse skipping mode v in = 3.6v l = 4.7 f efficiency vs input voltage efficiency vs output current efficiency vs output current input voltage (v) 2 efficiency (%) 75 80 5 7 3404 g01 70 60 85 65 34 6 90 95 8 burst mode operation v out = 2.5v l = 4.7 h i out = 100ma i out = 10ma i out = 1ma i out = 300ma i out = 0.1ma output current (ma) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 0.1 10 100 1000 3404 g02 0 1 v in = 3.6v v in = 3.6v v in = 4.2v v in = 4.2v pulse skipping mode burst mode operation v out = 1.8v l = 4.7 h output current (ma) 55 efficiency (%) 65 70 80 90 0.1 10 100 1000 3404 g03 1 75 60 50 85 l = 4.7 h l = 3.5 h burst mode operation v in = 6v v out = 2.5v
5 ltc3404 3404fb typical perfor a ce characteristics uw switch leakage vs temperature temperature ( c) ?0 switch leakage ( a) 25 3404 g13 2.0 1.0 ?5 0 50 0.5 0 2.5 1.5 75 100 125 main switch v in = 7v run = 0v synchronous switch burst mode operation switch leakage vs input voltage input voltage (v) 0 0 switch leakage (na) 0.2 0.4 0.6 0.8 24 6 8 3404 g20 1.0 1.2 13 5 7 synchronous switch main switch run = 0v pulse skipping mode operation start-up from shutdown dc supply current vs temperature temperature ( c) ?0 300 350 400 450 250 200 150 100 50 0 25 75 3404 g12 ?5 0 50 125 100 supply current ( a) pulse skipping mode burst mode operation v in = 3.6v v out = 1.5v 10 s/div v in = 4.2v v out = 1.5v l = 4.7 h c in = 10 f c out = 22 f i load = 30ma sw 5v/div i l 200ma/div v out 50mv/div ac coupled 3404 g14 500ns/div v in = 4.2v v out = 1.5v l = 4.7 h c in = 10 f c out = 22 f i load = 30ma sw 5v/div i l 100ma/div v out 10mv/div 3404 g15 40 s/div v in = 3.6v v out = 1.5v l = 4.7 h c in = 10 f c out = 22 f i load = 500ma run 2v/div i l 500ma/div v out 1v/div 3404 g16 input voltage (v) 1 0 r ds(on) ( ) 0.5 0.6 0.7 5678 3404 g09 0.4 0.3 0 0.1 2 3 4 0.2 0.9 0.8 synchronous switch main switch r ds(on) vs input voltage r ds(on) vs temperature dc supply current vs input voltage temperature ( c) ?0 25 0.3 r ds(on) ( ) 0.4 0.6 0.7 0.8 75 100 1.2 3404 g10 0.5 0 25 50 125 0.9 1.0 1.1 v in = 3v v in = 5v synchronous switch main switch input voltage (v) 0 dc supply current ( a) 200 500 2 4 5 3404 g11 100 400 300 250 150 50 450 350 3 6 78 v out = 1.8v pulse skipping mode burst mode operation
6 ltc3404 3404fb run (pin 1): run control input. forcing this pin below 0.4v shuts down the ltc3404. in shutdown all functions are disabled drawing < 1 a supply current. forcing this pin above 1.2v enables the ltc3404. do not leave run floating. i th (pin 2): error amplifier compensation point. the current comparator threshold increases with this control voltage. nominal voltage range for this pin is from 0.5v to 1.9v. v fb (pin 3): feedback pin. receives the feedback voltage from an external resistive divider across the output. gnd (pin 4): ground pin. sw (pin 5): switch node connection to inductor. this pin connects to the drains of the internal main and synchro- nous power mosfet switches. v in (pin 6): main supply pin. must be closely decoupled to gnd, pin 4. sync/mode (pin 7): external clock synchronization and mode select input. to synchronize with an external clock, apply a clock with a frequency between 1mhz and 1.7mhz. to select burst mode operation, tie to v in . grounding this pin selects pulse skipping mode. do not leave this pin floating. pll lpf (pin 8): output of the phase detector and control input of oscillator. connect a series rc lowpass network from this pin to ground if externally synchronized. if unused, this pin may be left open. uu u pi fu ctio s load step response load step response load step response 40 s/div v in = 3.6v v out = 1.5v l = 4.7 h c in = 10 f c out = 22 f i load = 200ma to 500ma pulse skipping mode v out 100mv/div i l 500ma/div i th 1v/div 3404 g17 40 s/div v in = 3.6v v out = 1.5v l = 4.7 h c in = 10 f c out = 22 f i load = 50ma to 500ma pulse skipping mode v out 100mv/div i l 500ma/div i th 1v/div 3404 g18 40 s/div v in = 3.6v v out = 1.5v l = 4.7 h c in = 10 f c out = 22 f i load = 50ma to 500ma burst mode operation v out 100mv/div i l 500ma/div i th 1v/div 3404 g19 typical perfor a ce characteristics uw
7 ltc3404 3404fb + + + + + ovdet ea + i rcmp + i comp 8 7 3 1 run pll lpf vco x y y = ??only when x is a constant ? burst defeat slope comp osc sync/mode 0.6v freq shift v ref 0.8v 0.85v g m = 0.5m 0.8v ref shutdown 0.55v 0.8v sleep v in v in v in v in i th sleep v fb en burst v in 2 s r rs latch switching logic and blanking circuit anti- shoot- thru q q 6 6 sw 5 gnd 3404 bd 4 p-ch p-ch n-ch fu ctio al diagra u u w operatio u main control loop the ltc3404 uses a constant frequency, current mode step-down architecture. both the main (p-channel mos- fet) and synchronous (n-channel mosfet) switches are internal. during normal operation, the internal top power mosfet is turned on each clock cycle when the oscillator sets the rs latch, and turned off when the current com- parator, i comp , resets the rs latch. the peak inductor current at which i comp resets the rs latch is controlled by the voltage on the i th pin, which is the output of error amplifier ea. the v fb pin, described in the pin functions section, allows ea to receive an output feedback voltage from an external resistive divider. when the load current increases, it causes a slight decrease in the feedback voltage, v fb , relative to the 0.8v internal reference, which in turn, causes the i th voltage to increase until the average inductor current matches the new load current. while the top mosfet is off, the bottom mosfet is turned on until either the inductor current starts to reverse as indicated by the current reversal comparator i rcmp , or the beginning of the next clock cycle. comparator ovdet guards against transient overshoots >6.25% by turning the main switch off and keeping it off until the fault is removed. burst mode operation the ltc3404 is capable of burst mode operation in which the internal power mosfets operate intermittently based on load demand. to enable burst mode operation, simply tie the sync/mode pin to v in or connect it to a logic high (v sync/mode > 1.5v). to disable burst mode operation and enable pwm pulse skipping mode, connect the sync/ mode pin to gnd. in this mode, the efficiency is lower at light loads, but becomes comparable to burst mode operation when the output load exceeds 50ma. the ad- vantage of pulse skipping mode is lower output ripple and less interference to audio circuitry.
8 ltc3404 3404fb figure 1. maximum output current vs input voltage supply voltage (v) 2.5 maximum output current (ma) 1200 1000 800 600 400 200 0 3.5 4.5 5.5 6.5 3404 ?f01 7.5 l = 4.7 h v out = 3.3v v out = 2.5v v out = 1.5v operatio u when the converter is in burst mode operation, the peak current of the inductor is set to approximately 250ma, even though the voltage at the i th pin indicates a lower value. the voltage at the i th pin drops when the inductor? average current is greater than the load requirement. as the i th voltage drops below approximately 0.55v, the burst comparator trips, causing the internal sleep line to go high and forces off both power mosfets. the i th pin is then disconnected from the output of the ea amplifier and held a diode voltage (0.7v) above ground. in sleep mode, both power mosfets are held off and a majority of the internal circuitry is partially turned off, reducing the quiescent current to 10 a. the load current is now being supplied solely from the output capacitor. when the output voltage drops, the i th pin reconnects to the output of the ea amplifier and the top mosfet is again turned on and this process repeats. short-circuit protection when the output is shorted to ground, the frequency of the oscillator is reduced to about 200khz, 1/7 the nominal frequency. this frequency foldback ensures that the inductor current has ample time to decay, thereby prevent- ing runaway. the oscillator? frequency will progressively increase to 1.4mhz (or the synchronized frequency) when v fb rises above 0.3v. frequency synchronization a phase-locked loop (pll) is available on the ltc3404 to allow the internal oscillator to be synchronized to an external source connected to the sync/mode pin. the output of the phase detector at the pll lpf pin operates over a 0v to 2.4v range corresponding to 1mhz to 1.7mhz. when locked, the pll aligns the turn-on of the top mos- fet to the rising edge of the synchronizing signal. when the ltc3404 is clocked by an external source, burst mode operation is disabled; the ltc3404 then operates in pwm pulse skipping mode. in this mode, when the output load is very low, current comparator i comp may remain tripped for several cycles and force the main switch to stay off for the same number of cycles. increasing the output load slightly allows constant frequency pwm operation to resume. this mode exhibits low output ripple as well as low audio noise and reduced rf interference while provid- ing reasonable low current efficiency. frequency synchronization is inhibited when the feedback voltage v fb is below 0.6v. this prevents the external clock from interfering with the frequency foldback for short- circuit protection. dropout operation when the input supply voltage decreases toward the output voltage, the duty cycle increases toward the maxi- mum on-time. further reduction of the supply voltage forces the main switch to remain on for more than one cycle until it reaches 100% duty cycle. the output voltage will then be determined by the input voltage minus the voltage drop across the internal p-channel mosfet and the inductor. low supply operation the ltc3404 is designed to operate down to an input supply voltage of 2.65v although the maximum allowable output current is reduced at this low voltage. figure 1 shows the reduction in the maximum output current as a function of input voltage for various output voltages. another important detail to remember is that at low input supply voltages, the r ds(on) of the p-channel switch increases. therefore, the user should calculate the power dissipation when the ltc3404 is used at 100% duty cycle with a low input voltage (see thermal considerations in the applications information section).
9 ltc3404 3404fb figure 2. maximum inductor peak current vs duty cycle duty cycle (%) 0 maximum inductor peak current (ma) 1100 1000 900 800 700 600 80 3404 f02 20 40 60 100 v in = 3.3v operatio u applicatio s i for atio wu uu slope compensation and inductor peak current slope compensation provides stability in constant fre- quency architectures by preventing subharmonic oscilla- tions at high duty cycles. it is accomplished internally by adding a compensating ramp to the inductor current signal at duty cycles in excess of 40%. as a result, the maximum inductor peak current is reduced for duty cycles > 40%. this is shown in the decrease of the inductor peak current as a function of duty cycle graph in figure 2. the basic ltc3404 application circuit is shown on the first page. external component selection is driven by the load requirement and begins with the selection of l followed by c in and c out . inductor value calculation the inductor selection will depend on the operating fre- quency of the ltc3404. the internal nominal frequency is 1.4mhz, but can be externally synchronized from 1mhz to 1.7mhz. the operating frequency and inductor selection are inter- related in that higher operating frequencies allow the use of smaller inductor and capacitor values. however, oper- ating at a higher frequency generally results in lower efficiency because of increased internal gate charge losses. the inductor value has a direct effect on ripple current. the ripple current i l decreases with higher inductance or frequency and increases with higher v in or v out . = ()( ) ? ? ? ? ? ? ? i fl v v v l out out in 1 1 (1) accepting larger values of i l allows the use of smaller inductors, but results in higher output voltage ripple and greater core losses. a reasonable starting point for setting ripple current is i l = 0.4(i max ). the inductor value also has an effect on burst mode operation. the transition to low current operation begins when the inductor current peaks fall to approximately 250ma. lower inductor values (higher i l ) will cause this to occur at lower load currents, which can cause a dip in efficiency in the upper range of low current operation. in burst mode operation, lower inductance values will cause the burst frequency to increase. inductor core selection once the value for l is known, the type of inductor must be selected. high efficiency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite, molypermalloy, or kool m cores. actual core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. as inductance increases, core losses go down. unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. ferrite designs have very low core losses and are pre- ferred at high switching frequencies, so design goals can concentrate on copper loss and preventing saturation. ferrite core material saturates ?ard,?which means that inductance collapses abruptly when the peak design cur- rent is exceeded. this results in an abrupt increase in
10 ltc3404 3404fb v fb gnd ltc3404 0.8v v out 6v r2 r1 3404 f03 figure 3. setting the ltc3404 output voltage applicatio s i for atio wu uu inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! kool m (from magnetics, inc.) is a very good, low loss core material for toroids with a ?oft?saturation character- istic. molypermalloy is slightly more efficient at high (>200khz) switching frequencies but quite a bit more expensive. toroids are very space efficient, especially when you can use several layers of wire, while inductors wound on bobbins are generally easier to surface mount. new designs for surface mount inductors are available from coiltronics, coilcraft, dale and sumida. c in and c out selection in continuous mode, the source current of the top mos- fet is a square wave of duty cycle v out /v in . to prevent large voltage transients, a low esr input capacitor sized for the maximum rms current must be used. the maxi- mum rms capacitor current is given by: ci vvv v in omax out in out in required i rms ? ? () [] 12 / this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is com- monly used for design because even significant deviations do not offer much relief. note that the capacitor manufacturer? ripple current ratings are often based on 2000 hours of life. this makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. always consult the manufacturer if there is any question. the selection of c out is driven by the required effective series resistance (esr). typically, once the esr require- ment is satisfied, the capacitance is adequate for filtering. the output ripple v out is determined by: ? + ? ? ? ? ? ? v i esr fc out l out 1 8 where f = operating frequency, c out = output capacitance and i l = ripple current in the inductor. the output ripple is highest at maximum input voltage since i l increases with input voltage. for the ltc3404, the general rule for proper operation is: c out required esr < 0.25 the choice of using a smaller output capacitance increases the output ripple voltage due to the frequency dependent term but can be compensated for by using capacitor(s) of very low esr to maintain low ripple voltage. the i th pin compensation components can be opti mized to provide stable high performance transient response regardless of the output capacitor selected. esr is a direct function of the volume of the capacitor. manufacturers such as taiyo-yuden, avx, kemet, sprague and sanyo should be considered for high performance capacitors. the poscap solid electrolytic chip capacitor available from sanyo is an excellent choice for output bulk capacitors due to its low esr/size ratio. once the esr requirement for c out has been met, the rms current rating generally far exceeds the i ripple(p-p) requirement. when using tantalum capacitors, it is critical that they are surge tested for use in switching power supplies. a good choice is the avx tps series of surface mount tantalum, available in case heights ranging from 2mm to 4mm. other capacitor types include kemet t510 and t495 series and sprague 593d and 595d series. consult the manufacturer for other specific recommendations. output voltage programming the output voltage is set by a resistive divider according to the following formula: vv r r out =+ ? ? ? ? ? ? 08 1 2 1 . (2) the external resistive divider is connected to the output, allowing remote voltage sensing as shown in figure 3.
11 ltc3404 3404fb applicatio s i for atio wu uu figure 5. phase-locked loop block diagram sync/ mode phase detector digital phase/ frequency detector 2.4v r lp c lp vco 3404 f05 pll lpf figure 4. relationship between oscillator frequency and voltage at pll lpf pin v ppl lpf (v) 0.4 oscillator frequency (mhz) 1.6 3404 ?f04 0.8 1.2 2.0 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.6 1.0 1.4 1.8 phase-locked loop and frequency synchronization the ltc3404 has an internal voltage-controlled oscillator and phase detector comprising a phase-locked loop. this allows the top mosfet turn-on to be locked to the rising edge of an external frequency source. the frequency range of the voltage-controlled oscillator is 1mhz to 1.7mhz. the phase detector used is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. this type of phase detec- tor will not lock up on input frequencies close to the har- monics of the v co center frequency. the pll hold-in range f h is equal to the capture range, f h = f c = 300khz and 400khz. the output of the phase detector is a pair of complemen- tary current sources charging or discharging the external filter network on the pll lpf pin. the relationship between the voltage on the pll lpf pin and operating frequency is shown in figure 4. a simplified block diagram is shown in figure 5. if the external frequency (v sync/mode ) is greater than 1.4mhz, the center frequency, current is sourced continuously, pulling up the pll lpf pin. when the external frequency is less than 1.4mhz, current is sunk continuously, pulling down the pll lpf pin. if the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. thus the voltage on the pll lpf pin is adjusted until the phase and frequency of the external and internal oscilla- tors are identical. at this stable operating point the phase comparator output is high impedance and the filter capacitor c lp holds the voltage. the loop filter components c lp and r lp smooth out the current pulses from the phase detector and provide a stable input to the voltage controlled oscillator. the filter component? c lp and r lp determine how fast the loop acquires lock. typically r lp = 10k and c lp is 2200pf to 0.01 f. when not synchronized to an external clock, the internal connection to the vco is disconnected. this disallows setting the internal oscillator frequency by a dc voltage on the v pll lpf pin. efficiency considerations the efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. efficiency can be expressed as: efficiency = 100% ?(l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percentage of input power. although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses in ltc3404 circuits: v in quiescent current and i 2 r losses. the v in quiescent current loss dominates the efficiency loss at very low load currents whereas the i 2 r loss dominates the efficiency loss at medium to high load currents. in a typical efficiency plot, the efficiency curve at
12 ltc3404 3404fb load current (ma) 0.1 1 0.00001 power lost (w) 0.001 1 10 100 1000 3404 f06 0.0001 0.01 0.1 v out = 1.5v v out = 2.5v v out = 3.3v v in = 4.2v l = 4.7 h burst mode operation figure 6. power lost vs load current applicatio s i for atio wu uu very low load currents can be misleading since the actual power lost is of no consequence as illustrated in figure 6. 1. the v in quiescent current is due to two components: the dc bias current as given in the electrical character- istics and the internal main switch and synchronous switch gate charge currents. the gate charge current results from switching the gate capacitance of the internal power mosfet switches. each time the gate is switched from high to low to high again, a packet of charge dq moves from v in to ground. the resulting dq/dt is the current out of v in that is typically larger than the dc bias current. in continuous mode, i gatechg = f(q t + q b ) where q t and q b are the gate charges of the internal top and bottom switches. both the dc bias and gate charge losses are proportional to v in and thus their effects will be more pronounced at higher supply voltages. 2. i 2 r losses are calculated from the resistances of the internal switches, r sw , and external inductor r l . in continuous mode the average output current flowing through inductor l is ?hopped?between the main switch and the synchronous switch. thus, the series resistance looking into the sw pin is a function of both top and bottom mosfet r ds(on) and the duty cycle (dc) as follows: r sw = (r ds(on)top )(dc) + (r ds(on)bot )(1 ?dc) the r ds(on) for both the top and bottom mosfets can be obtained from the typical performance charateristics curves. thus, to obtain i 2 r losses, simply add r sw to r l and multiply the result by the square of the average output current. other losses including c in and c out esr dissipative losses and inductor core losses generally account for less than 2% total additional loss. thermal considerations in most applications the ltc3404 does not dissipate much heat due to its high efficiency. but, in applications where the ltc3404 is running at high ambient tempera- ture with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maxi- mum junction temperature of the part. if the junction temperature reaches approximately 175 c, both power switches will be turned off and the sw node will become high impedance. to avoid the ltc3404 from exceeding the maximum junction temperature, the user will need to do some thermal analysis. the goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. the tempera- ture rise is given by: t r = (p d )( ja ) where p d is the power dissipated by the regulator and q ja is the thermal resistance from the junction of the die to the ambient temperature. the junction temperature, t j , is given by: t j = t a + t r where t a is the ambient temperature. as an example, consider the ltc3404 in dropout at an input voltage of 3v, a load current of 500ma, and an ambient temperature of 70 c. from the typical perfor- mance graph of switch resistance, the r ds(on) of the p-channel switch at 70 c is approximately 0.7 . there- fore, power dissipated by the part is: p d = i load 2 ?r ds(on) = 0.175w for the msop package, the ja is 150 c/ w. thus, the junction temperature of the regulator is: t j = 70 c + (0.175)(150) = 96 c
13 ltc3404 3404fb applicatio s i for atio wu uu figure 7. ltc3404 layout diagram + run i th v fb gnd pll lpf sync/mode sw ltc3404 c c2 c c1 r c c out 3404 f07 l1 v in bold lines indicate high current paths 1 2 3 4 8 7 6 5 optional + + v out v in r2 c in + r1 which is below the maximum junction temperature of 125 c. note that at higher supply voltages, the junction tempera- ture is lower due to reduced switch resistance (r ds(on) ). checking transient response the regulator loop response can be checked by looking at the load transient response. switching regulators take several cycles to respond to a step in load current. when a load step occurs, v out immediately shifts by an amount equal to ( i load ?esr), where esr is the effective series resistance of c out . i load also begins to charge or discharge c out , which generates a feedback error signal. the regulator loop then acts to return v out to its steady- state value. during this recovery time v out can be moni- tored for overshoot or ringing that would indicate a stabil- ity problem. the internal compensation provides adequate compensation for most applications. but if additional compensation is required, the i th pin can be used for external compensation using r c , c c1 as shown in figure 7. (the 47pf capacitor, c c2 , is typically needed for noise decoupling.) a second, more severe transient is caused by switching in loads with large (>1 f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. the only solution is to limit the rise time of the switch drive so that the load rise time is limited to approximately (25 ?c load ). thus, a 10 f capacitor charging to 3.3v would require a 250 s rise time, limiting the charging current to about 130ma. pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc3404. these items are also illustrated graphically in the layout diagram of figure 7. check the following in your layout: 1. are the signal and power grounds segregated? the ltc3404 signal ground consists of the resistive divider, the optional compensation network (r c and c c1 ) and c c2 . the power ground consists of the (? plate of c in , the (? plate of c out and pin 4 of the ltc3404. the power ground traces should be kept short, direct and wide. the signal ground and power ground should converge to a common node in a star- ground configuration. 2. does the v fb pin connect directly to the feedback resistors? the resistive divider r1/r2 must be con- nected between the (+) plate of c out and signal ground. 3. does the (+) plate of c in connect to v in as closely as possible? this capacitor provides the ac current to the internal power mosfets. 4. keep the switching node sw away from sensitive small signal nodes. design example as a design example, assume the ltc3404 is used in a single lithium-ion battery-powered cellular phone applica- tion. the input voltage will be operating from a maximum of 4.2v down to about 2.7v. the load current requirement is a maximum of 0.3a but most of the time it will be in standby mode, requiring only 2ma. efficiency at both low and high load currents is important. output voltage is 2.5v. with this information we can calculate l using equation (1), l fi v v v l out out in = () () ? ? ? ? ? ? ? 1 1 (3)
14 ltc3404 3404fb figure 8. single lithium-ion to 2.5v/0.3a regulator from design example v out 2.5v * ** *** 47pf 10 f*** cer 6.2 h* 887k 22 f** cer 412k ltc3404 run i th v fb gnd 8 7 6 5 1 2 3 4 pll lpf sync/mode v in sw v in 2.65v to 4.2v toko d63lcb a920cy-6r2m taiyo-yuden ceramic jmk325bj226mm taiyo-yuden ceramic lmk325bj106mn 3404 f08a 20pf typical applicatio s u v out 2.5v 0.6a c in *** 10 f cer 20pf 887k c out ** 22 f cer * ** *** 47pf 4.7 h* ltc3404 run i th v fb gnd 8 7 6 5 1 2 3 4 pll lpf sync/mode v in sw v in 3v to 4.2v toko d52lc a914byw-4r7m taiyo-yuden ceramic jmk325bj226mm taiyo-yuden ceramic lmk325bj106mn 3404 ta03 412k single li-ion to 2.5v/0.6a regulator using all ceramic capacitors output current (ma) efficiency (%) 95 90 85 80 75 70 0.1 10 100 1000 3404 f8b 1.0 v out = 2.5v l = 6.2 h v in = 3v v in = 4.2v v in = 3.6v applicatio s i for atio wu uu substituting v out = 2.5v, v in = 4.2v, i l =120ma and f = 1.4mhz in equation (3) gives: l v mhz ma v v h = ? ? ? ? ? ? ? = 25 1 4 120 1 25 42 6 . .( ) . . a 6.2 h inductor works well for this application. for best efficiency choose a 1a inductor with less than 0.25 series resistance. c in will require an rms current rating of at least 0.15a at temperature and c out will require an esr of less than 0.25 . in most applications, the requirements for these capacitors are fairly similar. for the feedback resistors, choose r1 = 412k. r2 can then be calculated from equation (2) to be: r v r k use out 2 08 1 1 875 5 8 = ? ? ? ? ? ? ? = . . ; 87k figure 8 shows the complete circuit along with its effi- ciency curve.
15 ltc3404 3404fb typical applicatio s u v out 2.5v 0.3a c in *** 10 f cer 20pf 887k c out ** 22 f cer 47pf 6.2 h* ltc3404 run i th v fb gnd 8 7 6 5 1 2 3 4 pll lpf sync/mode v in sw v in 2.65v to 6v 3404 ta06 412k * ** *** toko d63lcb a920cy-6r2m taiyo-yuden ceramic jmk325bj226mm taiyo-yuden ceramic lmk325bj106mn low noise 2.5v/0.3a regulator v out 2.5v 0.6a c in *** 10 f cer 20pf ext clock 1.7mhz 887k c out ** 22 f cer 47pf 4.7 h* 10k 0.01 f ltc3404 run i th v fb gnd 8 7 6 5 1 2 3 4 pll lpf sync/mode v in sw v in 3v to 6v 3404 ta04 412k * ** *** toko d52lc a914byw-4r7m taiyo-yuden ceramic jmk325bj226mm taiyo-yuden ceramic lmk325bj106mn externally synchronized 2.5v/0.6a regulator using all ceramic capacitors information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. ms8 package 8-lead plastic msop (ltc dwg # 05-08-1660 rev f) u package descriptio v out 1.8v 0.5a c in *** 10 f cer 20pf 887k c out ** 22 f cer 47pf 4.7 h* ltc3404 run i th v fb gnd 8 7 6 5 1 2 3 4 pll lpf sync/mode v in sw v in 2.7v to 6v 3404 ta04 698k * ** *** toko d52lc a914byw-4r7m taiyo-yuden ceramic jmk325bj226mm taiyo-yuden ceramic lmk325bj106mn 3- to 4-cell nicd/nimh to 1.8v/0.5a regulator using all ceramic capacitors msop (ms8) 0307 rev f 0.53 0.152 (.021 .006) seating plane note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.18 (.007) 0.254 (.010) 1.10 (.043) max 0.22 ?0.38 (.009 ?.015) typ 0.1016 0.0508 (.004 .002) 0.86 (.034) ref 0.65 (.0256) bsc 0 ?6 typ detail ? detail ? gauge plane 12 3 4 4.90 0.152 (.193 .006) 8 7 6 5 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) 0.52 (.0205) ref 5.23 (.206) min 3.20 ?3.45 (.126 ?.136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.42 0.038 (.0165 .0015) typ 0.65 (.0256) bsc
16 ltc3404 3404fb related parts part number description comments ltc1174/ltc1174-3.3 high efficiency step-down and inverting dc/dc converters monolithic switching regulators, i out to 450ma, ltc1174-5 burst mode operation ltc1265 1.2a, high efficiency step-down dc/dc converter constant off-time, monolithic, burst mode operation ltc1474/ltc1475 low quiescent current step-down dc/dc converters monolithic, i out to 250ma, i q = 10 a, 8-pin msop ltc1504a monolithic synchronous step-down switching regulator low cost, voltage mode i out to 500ma, v in from 4v to 10v ltc1622 low input voltage current mode step-down dc/dc controller high frequency, high efficiency, 8-pin msop ltc1626 low voltage, high efficiency step-down dc/dc converter monolithic, constant off-time, i out to 600ma, low supply voltage range: 2.5v to 6v ltc1627 monolithic synchronous step-down switching regulator constant frequency, i out to 500ma, secondary winding regulation, v in from 2.65v to 8.5v ltc1701 monolithic current mode step-down switching regulator constant off-time, i out to 500ma, 1mhz operation, v in from 2.5v to 5.5v ltc1707 monolithic synchronous step-down switching regulator 1.19v v ref pin, constant frequency, i out to 600ma, v in from 2.65v to 8.5v ltc1772 low input voltage current mode step-down dc/dc controller 550khz, 6-pin sot-23, i out up to 5a, v in from 2.2v to 10v ltc1877 high efficiency monolithic step-down regulator 550khz, ms8, v in up to 10v, i q = 10 a, i out to 600ma at v in = 5v ltc1878 high efficiency monolithic step-down regulator 550khz, ms8, v in up to 6v, i q = 10 a, i out to 600ma at v in = 3.3v linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com lt 0607 rev b ?printed in usa ? linear technology corporation 2000 typical applicatio s u 3- to 4-cell nicd/nimh to 3.3v/0.5a regulator using all ceramic capacitors single li-ion to 2.5v/0.5a regulator with precision 2.7v undervoltage lockout v out ? 3.3v 0.5a c in *** 10 f cer 20pf 887k c out ** 22 f cer 47pf 4.7 h* ltc3404 run i th v fb gnd 8 7 6 5 1 2 3 4 pll lpf sync/mode v in sw v in 2.7v to 6v 3404 ta06 280k * ** *** ? toko d52lc a914byw-4r7m taiyo-yuden ceramic jmk325bj226mm taiyo-yuden ceramic lmk325bj106mn v out connected to v in for 2.7v < v in < 3.3v v out 2.5v 0.6a c in *** 10 f cer 20pf 887k c out ** 22 f cer 47pf 4.7 h* ltc3404 run i th v fb gnd 8 7 6 5 1 2 3 4 pll lpf sync/mode v in sw ltc1540 gnd v in + in 8 7 6 5 1 2 3 4 out v + ref hys v in 2.7v to 4.2v 3404 ta08 412k 44.2k 1% 1.58m 1% 1.18m 1% 0.01 f 0.1 f 10k 2.37m 1% * ** *** toko d52lc a914byw-4r7m taiyo-yuden ceramic jmk325bj226mm taiyo-yuden ceramic lmk325bj106mn

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